1. Field of the Invention
Generally, the present disclosure relates to the fabrication of highly sophisticated integrated circuits including advanced transistor elements that comprise gate structures of increased capacitance including a high-k gate dielectric material.
2. Description of the Related Art
The fabrication of advanced integrated circuits, such as CPUs, storage devices, ASICs (application specific integrated circuits) and the like, requires the formation of a large number of circuit elements on a given chip area according to a specified circuit layout. In a wide variety of integrated circuits, field effect transistors represent one important type of circuit element that substantially determines performance of the integrated circuits. Generally, a plurality of process technologies are currently practiced for forming field effect transistors, wherein, for many types of complex circuitry, CMOS technology is one of the most promising approaches due to the superior characteristics in view of operating speed and/or power consumption and/or cost efficiency. During the fabrication of complex integrated circuits using CMOS technology, millions of transistors, i.e., N-channel transistors and P-channel transistors, are formed on a substrate including a crystalline semiconductor layer. A field effect transistor, irrespective of whether an N-channel transistor or a P-channel transistor is considered, typically comprises so-called PN junctions that are formed by an interface of highly doped regions, referred to as drain and source regions, with a slightly doped or non-doped region, such as a channel region, disposed adjacent to the highly doped regions. In a field effect transistor, the conductivity of the channel region, i.e., the drive current capability of the conductive channel, is controlled by a gate electrode formed adjacent to the channel region and separated therefrom by a thin insulating layer. The conductivity of the channel region, upon formation of a conductive channel due to the application of an appropriate control voltage to the gate electrode, depends on, among other things, the mobility of the charge carriers in the channel region.
The continuous shrinkage of critical dimensions of transistor elements has resulted in a gate length of field effect transistors of 50 nm and significantly less, thereby providing sophisticated semiconductor devices having enhanced performance and an increased packing density. The increase of electrical performance of the transistors is strongly correlated with a reduction of the channel length, which may result in an increased drive current and switching speed of the field effect transistors. On the other hand, the reduction of the channel length is associated with a plurality of issues in terms of channel controllability and static leakage currents of these transistors. It is well known that field effect transistors with a very short channel may require an increased capacitive coupling between the gate electrode structure and the channel region in order to provide the desired static and dynamic current flow controllability. Typically, the capacitive coupling is increased by reducing the thickness of the gate dielectric material, which is typically formed on the basis of a silicon dioxide-based material, possibly in combination with a nitrogen species, due to the superior characteristics of a silicon/silicon dioxide interface. Upon implementing a channel length of the above-identified order of magnitude, however, the thickness of the silicon dioxide-based gate dielectric material may reach values of 1.5 nm and less, which in turn may result in significant leakage currents due to a direct tunneling of the charge carriers through the very thin gate dielectric material. Since the exponential increase of the leakage currents upon further reducing the thickness of silicon dioxide-based gate dielectric materials is not compatible with the thermal power design requirements, other mechanisms have been developed so as to further enhance transistor performance and/or reduce the overall transistor dimensions.
For example, by creating a certain strain component in the channel region of silicon-based transistor elements, the charge carrier mobility and, thus, the overall conductivity of the channel may be enhanced. For a silicon material with a standard crystallographic configuration, i.e., a (100) surface orientation with the channel length direction oriented along a <110> equivalent direction, tensile strain in the current flow direction may enhance conductivity of electrons, thereby improving transistor performance of N-channel transistors. On the other hand, generating a compressive strain in the current flow direction may increase the mobility of holes and may, thus, provide superior conductivity in P-channel transistors. Consequently, a plurality of strain-inducing mechanisms have been developed in the past, which per se require a complex manufacturing sequence for implementing these techniques. Upon further device scaling, “internal” strain-inducing sources, such as an embedded strain-inducing semiconductor material, may represent a very efficient strain-inducing mechanism. For example, frequently, the incorporation of a compressive strain-inducing silicon/germanium alloy in the drain and source areas of P-channel transistors is applied in order to enhance performance of these transistors. For this purpose, in an early manufacturing stage, cavities are formed in the active region laterally adjacent to the gate electrode structure of the P-channel transistor, while the N-channel transistors are covered by a spacer layer. These cavities may be subsequently refilled with the silicon/germanium alloy on the basis of selective epitaxial growth techniques. During the etch process for forming the cavities and during the subsequent epitaxial growth process, the gate electrode of the P-channel transistor has to be encapsulated in order to not unduly expose sensitive materials of the gate electrode structure, such as a silicon-based electrode material, to the process ambient for forming the cavities and for selectively growing the silicon/germanium alloy. Thereafter, the gate electrode structures may be exposed and the further processing may be continued by forming drain and source regions in accordance with any appropriate process strategy.
Basically, the above-described strain-inducing mechanism is a very efficient concept for improving transistor performance of P-channel transistors, wherein the efficiency of the finally obtained strain in the channel region of the transistor, however, strongly depends on the internal strain level of the semiconductor alloy and on the lateral offset of this material from the channel region. Typically, the material composition of the strain-inducing semiconductor alloy is restricted by currently available sophisticated selective epitaxial deposition recipes, which, in the case of a silicon/germanium alloy, may presently not allow germanium concentrations of more than approximately 30 atomic percent. Consequently, a further improvement of the total strain in the channel region requires a reduction of the lateral offset of the silicon/germanium alloy from the channel region so that any protective spacer structures may have to be provided with a reduced width.
In addition to providing strain-inducing mechanisms in sophisticated field effect transistors, sophisticated gate electrode materials have also been proposed in order to overcome the restrictions of conventional silicon dioxide/polysilicon-based gate electrode structures. To this end, the conventional silicon dioxide-based gate dielectric material is replaced, at least partially, by a so-called high-k dielectric material, i.e., a dielectric material having a dielectric constant of 10.0 and higher, which may result in a desired high capacitance between the gate electrode and the channel region, while nevertheless a certain minimum physical thickness is provided so as to keep the resulting leakage currents at an acceptable level. For this purpose, a plurality of dielectric materials, such as hafnium oxid-based materials, zirconium oxide, aluminum oxide and the like, are available and may be used in sophisticated gate electrode structures. Furthermore, the polysilicon material may also be replaced, at least in the vicinity of the gate dielectric material, since typically polysilicon suffers from charge carrier depletion in the vicinity of the gate dielectric material, which may reduce the effective capacitance. Moreover, with sophisticated high-k gate dielectric materials, the work function of standard polysilicon materials and a corresponding doping may no longer be sufficient to provide the required electronic characteristics of the gate electrode material in order to obtain a desired threshold voltage of the transistors under consideration. For this reason, specific work function adjusting metal species, such as aluminum, lanthanum and the like, are typically incorporated in the gate dielectric material and/or in an appropriate electrode material in order to obtain a desired work function and also increase conductivity of the gate electrode material at least in the vicinity of the gate dielectric material.
Thus, a plurality of sophisticated process strategies have been developed, wherein, in some promising approaches, the sophisticated gate materials, such as a high-k dielectric material and a metal-containing electrode material, possibly including a work function adjusting metal species, may be provided in an early manufacturing stage in combination with a polysilicon material, thereby providing a high degree of compatibility with conventional process strategies for forming sophisticated field effect transistors. It turns out, however, that a reliable confinement of the sensitive material system including the high-k dielectric material and the metal-containing electrode material has to be guaranteed in order to avoid a shift in threshold voltage or any other variabilities of the sophisticated high-k metal gate electrode structures.
In an attempt to further enhance device performance of sophisticated field effect transistors, it has been proposed to combine sophisticated high-k metal gate electrode structures with a strain-inducing mechanism, for instance, by incorporating a strain-inducing semiconductor alloy in the active regions of the transistors. In this case, the encapsulation of the gate electrode structure of the transistor, which may require the incorporation of an embedded strain-inducing semiconductor alloy, may have to be implemented on the basis of detrimental requirements. On the one hand, the confinement of the gate electrode structure has to ensure integrity of the sensitive material system, for example, prior to, during and after the incorporation of the strain-inducing semiconductor material, and, on the other hand, a reduced thickness of any protective spacer elements, such as silicon nitride-based materials, is to be selected with reduced width in view of enhancing efficiency of the strain-inducing mechanism. Consequently, a compromise of thickness of the spacer elements and gain in performance of sophisticated transistors is typically applied.
In many conventional approaches, however, overall defectivity during the patterning of the sophisticated high-k metal gate electrode structures may require efficient wet chemical cleaning processes. For this purpose, an SPM (mixture of sulfuric acid and hydrogen peroxide) solution has proven to be a very efficient cleaning agent, which, however, “efficiently” removes metal-containing electrode materials, such as titanium nitride, as are provided in the sophisticated gate electrode structure. Omitting the cleaning step on the basis of SPM or providing a less efficient cleaning recipe may significantly increase the overall defectivity, thereby resulting in a significant yield loss. Using efficient SPM cleaning solutions, however, may result in significant gate failures in sophisticated semiconductor designs, as will be described in more detail with reference to FIGS. 1a-1f. 
FIG. 1a schematically illustrates a top view of a semiconductor device 100 according to a complex design. As shown, the device 100 or its design comprises an active region 102A, which is to be understood as a semiconductor region in which one or more transistors are to be formed. For example, the active region 102A is illustrated to comprise three transistors 150A including respective gate electrode structures 130A. The gate electrode structures 130A may include a complex material system including a high-k dielectric material and a metal-containing electrode material, as discussed above. Basically, the gate electrode structures 130A represent conductive lines extending across the active region 102A and are typically formed with an end portion thereof on an isolation region 102C, which laterally delineates the active region 102A and any other active regions (not shown). Moreover, according to design requirements, a gate electrode structure 130C may also extend above the isolation region 102C in close proximity to the active region 102A. It should be appreciated that a length of the gate electrode structures 130A, 130C may be 50 nm and less in sophisticated applications so that the distance between the gate electrode structure 130C and the active region 102A may be significantly less than the critical gate length. Furthermore, the transistors 150A may represent devices that require the incorporation of a strain-inducing semiconductor material, such as a silicon/germanium alloy, possibly in combination with a semiconductor alloy for appropriately adjusting the threshold voltage of the transistors 150A.
Consequently, upon forming the device 100 according to the geometric configuration as shown in FIG. 1a, a plurality of complex process steps are required for forming the isolation region 102C and the active region 102A, followed by a sophisticated patterning process for implementing the gate electrode structures 130A, 130C in combination with any processes for forming the semiconductor alloy as required for adjusting the threshold voltage of the transistors 150A. To this end, complex wet chemical cleaning recipes are typically applied, which may have a negative influence on the finally obtained device characteristics, which may even result in significant gate failures. For example, it has been observed that, in particular, the metal-containing electrode material of the sensitive material system in the gate electrode structures 130A, 130C is significantly damaged or missing, which may result in reduced performance or total failure of the corresponding transistor elements. For this reason, appropriate sidewall spacer structures or protective liners are provided immediately after patterning the gate electrode structures 130A, 130C in order to appropriately encapsulate the sensitive gate material system. Although this concept may significantly reduce the gate failures, nevertheless, advanced yield loss may occur, wherein it has been recognized that, in particular, critical areas 100C significantly contribute to any device failures. For example, one of the critical regions 100C is a gate electrode structure or gate line 130C that is positioned close to the active region 102A. Moreover, the end portions of the gate electrode structures 130A, which extend from the active region 102A into the isolation region 102C also represent critical zones in which inferior integrity of the sensitive gate materials is observed. It is believed that, in particular, a significant recessing of the isolation region 102C in the vicinity of the active region 102A contributes to a less efficient encapsulation of the gate electrode structures 130A, 130C, which may then result in significant yield loss during the further processing, as will be described in more detail with reference to FIGS. 1b-1f. 
FIG. 1b schematically illustrates a cross-sectional view of a semiconductor device 100 according to the section indicated as Ib in FIG. 1a. As illustrated, the device 100 comprises a substrate 101 and a semiconductor layer 102, which is typically provided in the form of a silicon material. The substrate 101 and the semiconductor layer 102 may form a silicon-on-insulator (SOI) architecture when a buried insulating material (not shown) is formed below the semiconductor layer 102. In other cases, a bulk configuration may be formed by the semiconductor layer 102 and the substrate 101, when the semiconductor layer 102 is a portion of a crystalline semiconductor material of the substrate 101. The semiconductor layer 102 typically comprises a plurality of active regions, such as the active region 102A, which are laterally delineated by the isolation region 102C. The isolation region 102C is typically comprised of silicon dioxide and may have a pronounced recessing 102R that is positioned close to the active region 102A. Furthermore, the gate electrode structures 130A, 130C are formed on the active region 102A and the isolation region 102C, respectively, and comprise a material system 131, which is to be understood as a gate dielectric material including a high-k dielectric material, such as hafnium oxide and the like, in combination with a conventional dielectric material, such as silicon oxynitride and the like. Moreover, typically, the material system 131 comprises a metal-containing cap or electrode material, such as titanium nitride, which may also include appropriate metal species in order to obtain the desired work function, as is also discussed above. Thus, the material system 131 typically comprises a plurality of individual material layers, wherein the specific number and composition of the various material layers depend on device and process requirements. Furthermore, the gate electrode structures 130A, 130C comprise a further electrode material 132, for instance in the form of a silicon material, followed by a dielectric cap material 133, such as a silicon nitride material, a silicon dioxide material, or a combination thereof and the like. Furthermore, a liner or spacer 134, for instance comprised of silicon nitride, is formed on the sidewalls of the materials 132 and 131 in order that, in particular, any sensitive materials in the system 131 are appropriately protected.
FIG. 1c schematically illustrates a cross-sectional view along the section Ic of FIG. 1a. Thus, as shown, the gate electrode structure 130A is formed above the active region 102A and extends with an end portion thereof into the isolation region 102C. Also in this area, the pronounced recess 102R is typically present and may have a significant influence on the final characteristics of the gate electrode structure 130A.
The semiconductor device 100 as shown in FIGS. 1b and 1c is formed on the basis of the following process techniques. The isolation region 102C is formed in the semiconductor layer 102 on the basis of well-established shallow trench isolation process techniques. Thereafter, appropriate masking regimes may be applied so as to incorporate a desired well dopant species in the various active regions, such as the active region 102A, thereby adjusting the basic transistor characteristics, such as conductivity type, threshold voltage and the like. As is well known, a plurality of cleaning processes may typically have to be applied which may result in a certain degree of material erosion in the isolation region 102C, wherein additional rework processes of the lithography processes may even further contribute to unwanted material erosion. Moreover, as discussed above, in some active regions, an additional semiconductor material (not shown) is frequently provided on the basis of selective epitaxial growth techniques, for instance for appropriately adjusting the threshold voltage of P-channel transistors, wherein the corresponding masking process in combination with the selective epitaxial growth techniques and the surface preparation processes associated therewith may result in a pronounced material loss in the isolation region 102C, in particular in the vicinity of the active region 102A when corresponding to a P-channel transistor. Thereafter, the further processing is continued by providing material layers for the system 131, possibly in combination with additional heat treatments so as to diffuse a work function adjusting metal species and the like. Finally, the material 132 and the cap material 133, possibly in combination with additional sacrificial materials, such as hard mask materials and the like, are deposited on the basis of appropriate process techniques. It should be appreciated that providing appropriate work function metals for P-channel transistors and N-channel transistors, respectively, may also involve respective patterning processes. Next, the complex layer stack is patterned by using sophisticated lithography and etch techniques followed by the deposition of a spacer layer or liner, which is subsequently patterned into the liner or spacer structure 134. To this end, various process strategies may be applied, wherein, in other device areas, the spacer or liner material may be patterned in a later manufacturing stage, while in other cases a dedicated liner material may be formed and patterned prior to depositing the spacer material which may be used for forming the structure 134.
With reference to FIGS. 1d-1f, a process sequence will be described as an example for illustrating a failure mechanism, in which the encapsulation of the gate electrode structures, such as the gate electrode structure 130C (FIG. 1b), may be insufficient and may result in pronounced yield loss. It should be appreciated, however, that a similar exposure of sensitive gate materials may also occur at the end portions of the gate electrode structure 130A caused by the pronounced recessing 102R, as shown in FIG. 1c. 
FIG. 1d schematically illustrates the device 100 during an etch process 103 for forming cavities 103A in the active region 102A adjacent to the isolation region 102C. As illustrated, the cap materials 133 and the liner 134 may act as an etch mask.
FIG. 1e schematically illustrates the device 100 during a cleaning process 104 in order to remove any etch byproducts and other contaminants, thereby, however, also contributing to a certain material erosion at exposed sidewall surface areas in the cavities 103A.
FIG. 1f schematically illustrates the semiconductor device 100 during a further cleaning process 106, which is typically performed prior to starting a selective epitaxial growth process in order to remove native oxides and the like. On the other hand, a certain degree of material erosion may occur in the cavities 103A so that a sidewall surface area 131S of the sensitive material system 131 may be exposed below the sidewall spacer structure 134 of the gate electrode structure 130C. Consequently, sensitive materials may be attacked and may be removed, depending on the cleaning or etch chemistry used. Furthermore, during the further processing, for instance upon epitaxially growing a strain-inducing semiconductor alloy in the cavities 103A, the sidewalls may not be efficiently covered, thereby even further contributing to material deterioration of the system 131 during the further processing.
Similarly, the recessed configuration of the isolation region 102C at or near the end portions of the gate electrode structure 130A (FIG. 1c) may also result in an exposure of any sensitive materials, thereby causing a significant shift of the overall material characteristics.
In view of the situation described above, the present disclosure relates to manufacturing techniques and semiconductor devices in which sophisticated high-k metal gate electrode structures may be formed in an early manufacturing stage, while avoiding or at least reducing the effects of one or more of the problems identified above.